An All-Electrical Floating-Gate Transmission Line Model Technique for Measuring Source Resistance in Heterostructure

A new technique for determining the parasitic source resistance in Heterostructure Field-Effect Transistors (HFET’s) is preManuscript received March 8, 1990; revised April 20, 1990. This work has been partially sponsored by an EECS Special Projects Fund from the MIT and by a TRW Scholarship from the MIT Undergraduate Research Opportunities Program. The review of this brief was arranged by Associate Editor S. Tiwari. The authors are with the Massachusetts Institute of Technology, Cambridge, MA 02139. IEEE Log Number 9037179. sented. The new technique is an improvement of the Floating-Gate Transmission Line Model (FGTLM), and uses purely electrical measurements, that is, there is no need to determine any critical lengths optically or by scanning electron microscopy. The technique is demonstrated in Ino.srAI,.,As/n+-InU,~~Ga~,~,As Metal-Insulator Doped semiconductor Field-Effect Transistors (MIDFET’s). The new technique holds great promise for automated measurements of source resistance in a manufacturing environment. The parasitic source and drain resistances severely limit the performance of Heterostructure Field-Effect Transistors (HFET’s). Specifically, since the source resistance R, degrades the transconductance g, its minimization is of great relevance. In order to do that, one must first be able to measure R, accurately. The Transmission-Line Model (TLM) method [ I ] , 121, has been the most popular technique for measuring R,. Also, a number of other techniques for evaluating the source resistance in metal-semiconductor field-effect transistors (MESFET’s) and modulation-doped field-effect transistors (MODFET’s) based on “end” resistance have been proposed [3]-[9]. Unfortunately, these techniques require simplistic assumptions on the behavior of gate current as a function of gate voltage. Typically, an exponential dependence is assumed [3][9]. However, a new, simple, and accurate measurement technique for extracting source resistance, called the Floating-Gate Transmission-Line Model (FGTLM) has been recently proposed and demonstrated by the authors [IO]. This new technique does not place any restrictive requirements on the gate current. The FGTLM technique accurately determines the values of the source and drain resistances by utilizing actual HFET structures of various gate lengths. The FGTLM provides two main advantages over the TLM. First, since measurements are carried out on the devices themselves, no special test structure that consumes valuable chip area is needed. Second, unlike a field-effect transistor structure, the TLM structure does not have a “gate,” and therefore, the spreading resistance due to current crowding at the source end of the gate cannot be correctly measured by the TLM. In our original FGTLM work [ lo] , the actual dimensions of the FET’s were determined by using a scanning electron microscope (SEM) with a precision of 0.1 pm. As such, the measurement techniques utilized in the FGTLM were not purely electrical but involved microscopy techniques as well. This is a serious drawback for the FGTLM, particularly from a manufacturing viewpoint where fully automated testing is essential. The TLM suffers from the same drawback. In this brief we propose and demonstrate a new approach to our earlier work in which the need for detailed microscopy measurement techniques is completely eliminated. Thus our new approach, unlike the conventional TLM, can now be fully automated. Fig. 1 is a linear resistive network which schematically represents a generic HFET with either a two-dimensional electron gas o r a doped channel, biased in the linear mode of operation [lo]. Using the FGTLM technique, floating-gate measurements of gatesource, gate-drain, and drain-source resistances are carried out [IO]. For example, the gate-source resistance with the gate floating, R,,(fg), is measured by injecting a small current from source to drain, and measuring the voltage drop between gate and source, with a high-impedance voltmeter. Similarly for other resistances. By inspection of Fig. 1, one finds [ I O ] ’